There are two important aspects of developing application-specific integrated circuit (ASIC) simulation and verification environments. One such aspect is that given the input to a device under test (DUT), one must be able to predict the output such that the simulation environment can check (or scoreboard) the predicted output versus the actual output to provide for the determination of correct operation of the DUT. Another such aspect is that, as ASICs gain complexity, human debuggability of simulations becomes a core concern. Many types of ASIC simulations have significant randomness in their stimulus (to gain coverage), may have large run-times, and have complex processing, resulting in simulations that are very complex to debug when simulation output mismatches occur. Thus, increasing the debuggability of simulations becomes a core contributor to the productivity of an ASIC development team.
Many ASICs and ASIC simulations are packet oriented. Examples of packet oriented ASIC simulations are router devices where the DUT performs straightforward routing and possibly minor content manipulation of packets as they traverse the DUT. Often, the DUT will internally re-order packets (i.e., injected packet stimulus) causing a simple packet expectation to not be possible. When developing simulation and verification environments for these types of DUTs, the common problem is how to correlate expected packet output with injected packet stimulus.
A conventional technique for carrying out such correlation is to use all the fields within the packet that are expected not to be modified in the DUT traversal to create a unique temporal signature for the packet. By carefully constructing the packet stimulus, one can create the desired interesting functional stimulus of the DUT and guarantee that the packet stimulus satisfies a temporal signature uniqueness property. The temporal signature refers to a tag of a specific bit pattern that is only valid for a specific span of time, usually until it is received and processed by the output processing side of the simulation. Thereafter, that specific bit pattern can be re-used for another transaction tag. In this manner, the simulation environment can pair up packet stimulus with observed packet output from the DUT during scoreboard processing to achieve packet checking and enables human debugging mechanism by providing means for identification and correlation of packets when debugging the ASIC simulation.
This technique of creating a unique temporal signature, however, is not applicable to DUTs that perform arbitrary processing and re-mapping on the incoming packets, such as that performed by transaction-oriented ASICs. For example, in a typical transaction flow of a probe filtering unit (PFU), debugging of a corresponding ASIC simulation has a number of adverse considerations. One adverse consideration is that packets output by the DUT may not have any obvious correlation to the input packet (e.g., the DUT may receive a packet of type A, but output a packet of type B). Another adverse consideration is that, even though the packets contain a tag, sophisticated DUTs may retag the packet during processing, causing the output packets seen by the simulation environment not to be correlatable to the input packets. Retagging of the packets creates problems for the simulation environment because the simulation environment is then unable to compute the correctness of the generated DUT output because it can't stitch together a cohesive transaction from the observed packet outputs. Additionally, such retagging creates problems for developers because there is no sub-string to search for in simulation logs causing there to be insufficient information for allowing packets to be reliably assigned to the transactions that they compose. Thus, based on these adverse considerations and their resulting drawbacks, the effectiveness of this technique of creating a unique temporal signature has limitations with respect to transaction-oriented ASICs.
Conventional approaches for facilitating simulation of transaction-oriented ASICs often include checkers (i.e., functions for checking expected results) that look at the end results of a transaction. For example, in the case of cache coherency processing ASICs, a shadow memory checker would be utilized for ensuring that cache coherency is maintained. In this manner, the end result is checked, but the individual transactions and packets cannot be checked. Furthermore, humans have a very hard debugging problem without having synthesized global transaction tags.
For behavioral simulations (i.e., non-register transfer level simulations), a conventional approach to facilitating such simulation is to extend the packet in the software simulation to have a globally unique transaction tag. The behavioral simulations can be modified so that as the packets flow across the behavioral DUT, it carries across the transaction tag from the input packet to the generated packets. The transaction tag is generated by the simulation environment to be globally unique in the simulation (such as an incremented transaction counter). In this manner, simulation checkers can be developed to correlate and score transactions, and the transaction tag is output by simulation logging to allow humans to “easily” debug simulations. However, this technique is often not possible with the actual register transfer level (RTL) simulation because the RTL simulation defines the actual signals and actual synthesizable logic for the ASIC and the size of a packet generally cannot be extended to include debug-oriented data.
Therefore, an approach for facilitating simulation and/or lab bring-up of transaction-oriented hardware in a manner that overcomes drawbacks associated with conventional approaches for facilitating simulation and/or lab bring-up of transaction-oriented hardware would be useful, advantageous and novel.